This feels like a bad solution. At least the STM32H7 line has SPI slave functionality in hardware, no need for PIO. The h7a3 can do full-duplex at 45 MHz in the datasheet. I've been able to overclock the SPI master, so 45 is likely conservative. So that's 3x faster reads. Writes up to 100 MHz, almost 5x faster. And then no PIO programming. I guess you'd have to do a bit of work with software to get DMA going during the dummy cycles, so maybe the read command wouldn't work, but that seems like a worthwhile tradeoff for such a bit performance improvement. It also looks like this library fully utilizes a core to meet latency needs? That's a bit much.
The cheapest STM32H7 costs about 4x more than RP2040 and runs at 5x the clock, so the fact that it would be 5x faster doesn’t imply a defect in this library.
This feels like a bad solution. At least the STM32H7 line has SPI slave functionality in hardware, no need for PIO. The h7a3 can do full-duplex at 45 MHz in the datasheet. I've been able to overclock the SPI master, so 45 is likely conservative. So that's 3x faster reads. Writes up to 100 MHz, almost 5x faster. And then no PIO programming. I guess you'd have to do a bit of work with software to get DMA going during the dummy cycles, so maybe the read command wouldn't work, but that seems like a worthwhile tradeoff for such a bit performance improvement. It also looks like this library fully utilizes a core to meet latency needs? That's a bit much.
The cheapest STM32H7 costs about 4x more than RP2040 and runs at 5x the clock, so the fact that it would be 5x faster doesn’t imply a defect in this library.